1. Field of the Invention
The present invention relates to an improved timer circuit and more particularly to a timer circuit with minimized power consumption.
2. Brief Description of the Prior Art
ID a prior art timer circuit, a built-in counter responding to a certain input signal counts a train of pulse signals from an oscillator. In addition, a built-in signal processor receiving the counter output produces a timer signal corresponding to the counting duration of the counter. Generally, the timing of application of an input signal varies according to the device in which the timer circuit is incorporated. Therefore, the circuit must be in standby condition at all times, i.e. it must always be ready to function properly irrespective of the timing of application of the input signal.
In accordance with the above, the timer circuit is designed so that in the standby condition a source voltage is continuously applied to its respective components, including the oscillator, the counter, and the signal processor. Thus if an input signal is not applied for a long time, the standby condition of the timer circuit inevitably results in costly power consumption.